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VFPU Register Mapping

The psp's VFPU (Vector Floating Point Unit) is a coprocessor that can perform quite a few useful operations. The main purpose of it is vector and matrix processing, but it also supports trigonemtric functions and other mathematical operations, conversions, and mathematical constants.

The VFPU has 128 single precision floating point registers (IEEE 754), but they are arranged and accessed in various ways that make it very flexible. Many of the instructions for the VFPU support operations on:

And if that weren't enough, it can work with matrices in normal or transposed orders.

The registers are grouped into 8 blocks of 16 registers each. This gives you enough room to work with 8 4x4 matrices, 8 3x3 matrices, 32 2x2 matrices. Or you can store up to 32 quad vectors, 40 triple vectors, 64 paired vectors, or 128 single values.

The register names you use on the VFPU depends highly on the instruction being performed, and can quickly become a nightmare when trying to figure out how to access or modify certain registers. Register names are numbered with 3 digits: Matrix, Column and Row. The tables below show how single, pair, triple, quad and matrix registers are mapped within a single 16 register block

Single Register
Quad Columns
Quad Rows
4x4 Matrix
4x4 Transpose Matrix
Triple Columns
Triple Rows
3x3 Matrix
3x3 Transpose Matrix
Pair Columns
Pair Rows
2x2 Matrix
2x2 Transpose Matrix
S000
S010
S020
S030
S001
S011
S021
S031
S002
S012
S022
S032
S003
S013
S023
S033
C000
C010
C020
C030
R000
R001
R002
R003
M000
E000
C000
C010
C020
C030
C001
C011
C021
C031
R000
R001
R002
R003
R010
R011
R012
R013
M000
M001
M010
M011
E000
E001
E010
E011
C000
C010
C020
C030
C002
C012
C022
C032
R000
R001
R002
R003
R020
R021
R022
R023
M000
M020
M002
M022
E000
E020
E002
E022

Repeat all of the above with the other 7 blocks of registers. Just change the first digit of the register names to work on a different set

Reading/writing data to the VFPU

There are 6 instructions that are used to read or write values into the VFPU registers

lv.*/sv.* read or write to ram using a general purpose register as a base pointer and an immediate offset value. Note that the address being read from or written to must be 16 byte aligned for lv.q/sv.q. Because of the amount of bits encoded in these instructions, the VFPU registers you can access are limited. You are limited to accessing only rows or columns in the VFPU, so you cant load to any arbitrary register. The tables below show which registers can be accessed with these instructions:

lv.q / sv.q (4 registers)
lv.s / sv.s (1 register)
C000
C010
C020
C030
C100
C110
C120
C130
C200
C210
C220
C230
C300
C310
C320
C330
C400
C410
C420
C430
C500
C510
C520
C530
C600
C610
C620
C630
C700
C710
C720
C730
R000
R001
R002
R003
R100
R101
R102
R103
R200
R201
R202
R203
R300
R301
R302
R303
R400
R401
R402
R403
R500
R501
R502
R503
R600
R601
R602
R603
R700
R701
R702
R703
C000
C010
C020
C030
C100
C110
C120
C130
C200
C210
C220
C230
C300
C310
C320
C330
C400
C410
C420
C430
C500
C510
C520
C530
C600
C610
C620
C630
C700
C710
C720
C730
R000
R001
R002
R003
R100
R101
R102
R103
R200
R201
R202
R203
R300
R301
R302
R303
R400
R401
R402
R403
R500
R501
R502
R503
R600
R601
R602
R603
R700
R701
R702
R703