This page is a copy of: http://bradburn.net/mr.mr/vfpu.html

VFPU Register Mapping

The psp's VFPU (Vector Floating Point Unit) is a coprocessor that can perform quite a few useful operations. The main purpose of it is vector and matrix processing, but it also supports trigonemtric functions and other mathematical operations, conversions, and mathematical constants.

The VFPU has 128 single precision floating point registers (IEEE 754), but they are arranged and accessed in various ways that make it very flexible. Many of the instructions for the VFPU support operations on:

• a single register
• a pair of registers
• three registers
• four regiters
• 2x2 matrix
• 3x3 matrix
• 4x4 matrix

And if that weren't enough, it can work with matrices in normal or transposed orders.

The registers are grouped into 8 blocks of 16 registers each. This gives you enough room to work with 8 4x4 matrices, 8 3x3 matrices, 32 2x2 matrices. Or you can store up to 32 quad vectors, 40 triple vectors, 64 paired vectors, or 128 single values.

The register names you use on the VFPU depends highly on the instruction being performed, and can quickly become a nightmare when trying to figure out how to access or modify certain registers. Register names are numbered with 3 digits: Matrix, Column and Row. The tables below show how single, pair, triple, quad and matrix registers are mapped within a single 16 register block

Repeat all of the above with the other 7 blocks of registers. Just change the first digit of the register names to work on a different set

Reading/writing data to the VFPU

There are 6 instructions that are used to read or write values into the VFPU registers

• lv.s - load single value from unaligned ram to single register
• lv.q - load quad value from ram to quad register
• ulv.q - load quad value from unaligned ram to quad register
• sv.s - store single value to unaligned ram from single register
• sv.q - store quad value to ram from quad register
• usv.q - store quad value to unaligned ram from quad register

lv.*/sv.* read or write to ram using a general purpose register as a base pointer and an immediate offset value. Note that the address being read from or written to must be 16 byte aligned for lv.q/sv.q. Because of the amount of bits encoded in these instructions, the VFPU registers you can access are limited. You are limited to accessing only rows or columns in the VFPU, so you cant load to any arbitrary register. The tables below show which registers can be accessed with these instructions: