PSP VFPU docuwiki

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FrancesRussell — 2010-06-03T23:48:47+02:00

This is the project page for the PSP VFPU documentation project. The original starter of this project was hlide. The original document creation thread can be found here: Please visit the index for getting an overview of the currently documented VFPU ops.

ops:vhdp

hlide — 2008-07-08T23:45:39+02:00

vhdp.q/t/p Calculates the homogeneous dot product of vs and vt and stores the result in vd.s Usage: vhdp.q/t/p vd.s, vs, vt { vd.s = vt[|q/t/p|]; for (i = 0; i < |q/t/p|-1; ++i) vd.s += vs[i] * vt[i]; } clock ticks latency vhdp.q/t/p 1 7

ops:vdot

hlide — 2008-07-08T23:43:26+02:00

vdot.q/t/p Calculates the vector dot product of vs and vt and stores the result in vd.s Usage: vdot.q/t/p vd.s, vs, vt { vd.s = 0; for (i = 0; i < |q/t/p/s|; ++i) vd.s += vs[i] * vt[i]; } clock ticks latency vdot.q/t/p 1 7

ops:vpfxd

hlide — 2008-07-08T23:39:25+02:00

vpfxd [] Alters the writing contents of a single precision float vector vd in the next non-prefix instruction. Can be used as a prefix instruction or as a postfix operand for vd. Usage as prefix instruction: vpfxd ?0, ?1, ?2, ?3 Example as postfix operand:

ops:vpfxt

hlide — 2008-07-08T23:34:48+02:00

vpfxt [] Alters the reading contents of a single precision float vector vt in the next non-prefix instruction. Can be used as a prefix instruction or as a postfix operand for vt. Usage as prefix instruction: vpfxt ?0, ?1, ?2, ?3 Example as postfix operand:

ops:vpfxs

hlide — 2008-07-08T23:32:20+02:00

vpfxs [] Alters the reading contents of a single precision float vector vs in the next non-prefix instruction. Can be used as a prefix instruction or as a postfix operand for vs. Usage as prefix instruction: vpfxs ?0, ?1, ?2, ?3 Example as postfix operand:

ops:vcmp

hlide — 2007-07-17T00:58:38+02:00

vcmp.q/t/p/s Compare each component of the single precision float vector vd to the same component of vs and assigned VFPU_CC according to their comparison results. Type single-cycle instruction Description vcmp.q/t/p/s cn2, vd, vs (where cn2 = EQ/NE/LT/LE/GT/GE) { for (i = 0; i < 5; ++i) VFPU_CC[i] = 0; VFPU_CC[5] = 1; for (i = 0; i < |q/t/p|; ++i) VFPU_CC[i] = bcmp(cn2, vs[i], vt[i]); // cn2 = EQ/NE/LE/LT/GE/GT for (i = 0; i < |q/t/p|; ++i) { VFPU_CC[4] ||= VFPU…

ops:lv_q

hlide — 2007-07-17T00:52:27+02:00

lv.q Loads a 16-byte long value from memory into a quad vfpu register. Type single-cycle instruction Description lv.q vd, offset(rm) { vd[0] = *((uint32 *)(rm + offset + 0)); vd[1] = *((uint32 *)(rm + offset + 4)); vd[2] = *((uint32 *)(rm + offset + 8)); vd[3] = *((uint32 *)(rm + offset + 12)); }

ops:lv_s

hlide — 2007-07-17T00:51:59+02:00

lv.s Loads a 4-byte long value from memory into a single vfpu register. Type single-cycle instruction Description lv.s vd.s, offset(rm) { vd.s = *((uint32 *)(rm + offset)); } rm is a general purpose register holding a memory address. offset is optional.

ops:mtv

hlide — 2007-07-17T00:48:26+02:00

mtv Copies a general purpose register into a scalar vfpu register. Type single-cycle instruction Description mtv rt, vs.s { vs.s = rt; // rt is general purpose register } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 1 3

ops:mfv

hlide — 2007-07-17T00:48:02+02:00

mfv Copies a scalar vfpu register into a general purpose register. Type interlock instruction Description mfv rt, vs.s { rt = vs.s; // rt is general purpose register } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 6 0

ops:bvtl

hlide — 2007-07-17T00:47:40+02:00

bvtl Branch a label if condition code is true. Type CPU interlock instruction Description bvtl cc, label { if (VFPU_CC[cc] == 1) { execute branch delay instruction at PC + 4; PC = PC + 4 + label; } } condition code is a numerical integer ranging between 0 and 5 :