PSP VFPU docuwiki ops

ops:bvf

2007-07-17T00:47:08+02:00

bvf Branch a label if condition code is false. Type CPU interlock instruction Description bvf cc, label { execute branch delay instruction at PC + 4; if (VFPU_CC[cc] == 0) PC = PC + 4 + label; } condition code is a numerical integer ranging between 0 and 5 :

ops:bvfl

2007-07-17T00:43:06+02:00

bvfl Branch a label if condition code is false. Type CPU interlock instruction Description bvfl cc, label { if (VFPU_CC[cc] == 0) { execute branch delay instruction at PC + 4; PC = PC + 4 + label; } } condition code is a numerical integer ranging between 0 and 5 :

ops:bvt

2007-07-17T00:43:36+02:00

bvt Branch a label if condition code is true. Type CPU interlock instruction Description bvt cc, label { execute branch delay instruction at PC + 4; if (VFPU_CC[cc] == 1) PC = PC + 4 + label; } condition code is a numerical integer ranging between 0 and 5 :

ops:bvtl

2007-07-17T00:47:40+02:00

bvtl Branch a label if condition code is true. Type CPU interlock instruction Description bvtl cc, label { if (VFPU_CC[cc] == 1) { execute branch delay instruction at PC + 4; PC = PC + 4 + label; } } condition code is a numerical integer ranging between 0 and 5 :

ops:lv_q

2007-07-17T00:52:27+02:00

lv.q Loads a 16-byte long value from memory into a quad vfpu register. Type single-cycle instruction Description lv.q vd, offset(rm) { vd[0] = *((uint32 *)(rm + offset + 0)); vd[1] = *((uint32 *)(rm + offset + 4)); vd[2] = *((uint32 *)(rm + offset + 8)); vd[3] = *((uint32 *)(rm + offset + 12)); }

ops:lv_s

2007-07-17T00:51:59+02:00

lv.s Loads a 4-byte long value from memory into a single vfpu register. Type single-cycle instruction Description lv.s vd.s, offset(rm) { vd.s = *((uint32 *)(rm + offset)); } rm is a general purpose register holding a memory address. offset is optional.

ops:mfv

2007-07-17T00:48:02+02:00

mfv Copies a scalar vfpu register into a general purpose register. Type interlock instruction Description mfv rt, vs.s { rt = vs.s; // rt is general purpose register } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 6 0

ops:mfvc

2007-03-18T01:54:27+02:00

mfvc Synopsys Copies a vfpu control register into a general purpose register. Type interlock instruction Description mfvc rt, vcr { rt = vcr; // vcr is vfpu control register } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 6 0 VFPU Control Registers register name purpose 128 VFPU_PFXS Source prefix stack 129 VFPU_PFXT Target prefix stack …

ops:mtv

2007-07-17T00:48:26+02:00

mtv Copies a general purpose register into a scalar vfpu register. Type single-cycle instruction Description mtv rt, vs.s { vs.s = rt; // rt is general purpose register } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 1 3

ops:mtvc

2007-03-18T01:50:26+02:00

mtvc Synopsys Copies a general purpose register into a vfpu control register. Category single-cycle instruction Usage mtvc rt, vcr { vcr = rt; // vcr is vfpu control register } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 1 3 VFPU Control Registers register name purpose 128 VFPU_PFXS Source prefix stack 129 VFPU_PFXT Target prefix stack …

ops:sv_q

2006-11-21T21:26:52+02:00

sv.q Stores a 16-byte long value from a quad vfpu register into memory. Usage: sv.q vd, offset(rm) { *(rm + offset + 0) = vd[0]; *(rm + offset + 4) = vd[1]; *(rm + offset + 8) = vd[2]; *(rm + offset + 12) = vd[3]; } rm is a general purpose register holding a memory address (aligned to 16 bytes). offset is optional. offset(rm) must be a multiple of 16.

ops:sv_s

2006-11-21T21:24:43+02:00

sv.s Stores a 4-byte long value from a single vfpu register into memory. Usage: sv.s vd.s, offset(rm) { *(rm + offset) = vd.s; } rm is a general purpose register holding a memory address. offset is optional. sv.s clock ticks latency (cache) ? ? (memory) ? ?

ops:ulv_q

2006-11-21T21:28:40+02:00

ulv.q Loads a 16-byte long value from unaligned memory into a quad vfpu register. Usage: ulv.q vd, offset(rm) { vd[0] = *(rm + offset + 0); vd[1] = *(rm + offset + 4); vd[2] = *(rm + offset + 8); vd[3] = *(rm + offset + 12); } this is not a real instruction but an alias to output a pair of lvl/lvr instructions.

ops:usv_q

2006-11-21T21:28:55+02:00

usv.q Stores a 16-byte long value (16 bytes) from a quad vfpu register into unaligned memory. Usage: usv.q vd, offset(rm) { *(rm + offset + 0) = vd[0]; *(rm + offset + 4) = vd[1]; *(rm + offset + 8) = vd[2]; *(rm + offset + 12) = vd[3]; }

ops:vabs

2006-11-22T14:36:42+02:00

vabs.q/t/p/s Computes the absolute value of each component of the single precision float vector vs and stores them into vd. Usage: vabs.q/t/p/s vd, vs { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = |vs[i]|; } clock ticks latency vabs.q/t/p/s 1 0

ops:vadd

2006-11-22T15:11:18+02:00

vadd.q/t/p/s Adds each component of the single precision float vector vs to the same component of vt and stores them into vd. Usage: vadd.q/t/p/s vd, vs, vt { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = vs[i] + vt[i]; } clock ticks latency vadd.q/t/p/s 1 0

ops:vc2i

2007-03-18T13:57:38+02:00

vc2i.s Converts four packed 8-bit signed char values in vs to four 8.24 fixed-point integer values in vd. Usage: vc2i.s vd.q, vs.s { vd.q[0] = ((vs.s[0] ) & 0xff) << 24; vd.q[1] = ((vs.s[0] >> 8) & 0xff) << 24; vd.q[2] = ((vs.s[0] >> 16) & 0xff) << 24; vd.q[3] = ((vs.s[0] >> 24) & 0xff) << 24; }

ops:vcmp

2007-07-17T00:58:38+02:00

vcmp.q/t/p/s Compare each component of the single precision float vector vd to the same component of vs and assigned VFPU_CC according to their comparison results. Type single-cycle instruction Description vcmp.q/t/p/s cn2, vd, vs (where cn2 = EQ/NE/LT/LE/GT/GE) { for (i = 0; i < 5; ++i) VFPU_CC[i] = 0; VFPU_CC[5] = 1; for (i = 0; i < |q/t/p|; ++i) VFPU_CC[i] = bcmp(cn2, vs[i], vt[i]); // cn2 = EQ/NE/LE/LT/GE/GT for (i = 0; i < |q/t/p|; ++i) { VFPU_CC[4] ||= VFPU…

ops:vcst

2006-12-14T13:49:52+02:00

vcst.q/t/p/s Load a constant into vd. Usage: vcst.q/t/p/s vd, index_constant { float vpfu_special_constant[] = { 0, Inf, // VFPU_HUGE SQRT(2), // VFPU_SQRT2 SQRT(1/2), // VFPU_SQRT1_2 2/SQRT(PI), // VFPU_2_SQRTPI 2/PI, // VFPU_2_PI 1/PI, // VFPU_1_PI PI/4, // VFPU_PI_4 PI/2, // VFPU_PI_2 PI, // VFPU_PI e, // VFPU_E log2(e), // VFPU_LOG2E log10(e), // VFPU_LOG10E ln(2), /…

ops:vdiv

2006-11-22T15:10:38+02:00

vdiv.q/t/p/s Divides each component of the single precision float vector vs by the same component of vt and stores them into vd. Usage: vdiv.q/t/p/s vd, vs, vt { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = vs[i] / vt[i]; } clock ticks latency vdiv.q 56 30 vdiv.t 42 ? vdiv.p 28 ? vdiv.s 14 ?

ops:vdot

2008-07-08T23:43:26+02:00

vdot.q/t/p Calculates the vector dot product of vs and vt and stores the result in vd.s Usage: vdot.q/t/p vd.s, vs, vt { vd.s = 0; for (i = 0; i < |q/t/p/s|; ++i) vd.s += vs[i] * vt[i]; } clock ticks latency vdot.q/t/p 1 7

ops:vhdp

2008-07-08T23:45:39+02:00

vhdp.q/t/p Calculates the homogeneous dot product of vs and vt and stores the result in vd.s Usage: vhdp.q/t/p vd.s, vs, vt { vd.s = vt[|q/t/p|]; for (i = 0; i < |q/t/p|-1; ++i) vd.s += vs[i] * vt[i]; } clock ticks latency vhdp.q/t/p 1 7

ops:viim

2006-12-14T13:35:37+02:00

viim.q/t/p/s Load immediate integer converted as a float into vd. Usage: viim.q/t/p/s vd, immediate { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = 1.0*immediate; } immediate is an integer value between -32768 and 32767 converted as a float when loaded

ops:vmax

2006-11-21T17:48:12+02:00

vmax.q/t/p/s Stores the four/three/two/one maximal single precision float value(s) of vs and vt into vd. Usage: vmax.q/t/p/s vd, vs, vt { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = max(vs[i], vt[i]); } clock ticks latency vmax.q/t/p/s 1 0

ops:vmfvc

2007-03-18T02:01:53+02:00

vmfvc Synopsys Copies a vfpu control register into a scalar vfpu register. Type single-cycle instruction Description vmfvc vcr, vs.s { vs.s = vcr; } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 1 3 VFPU Control Registers register name purpose 128 VFPU_PFXS Source prefix stack 129 VFPU_PFXT Target prefix stack 130 VFPU_PFXD Destin…

ops:vmin

2006-11-21T17:48:25+02:00

vmin.q/t/p/s Stores the four/three/two/one minimal single precision float value(s) of vs and vt into vd. Usage: vmin.q/t/p/s vd, vs, vt { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = min(vs[i], vt[i]); } clock ticks latency vmin.q/t/p/s 1 0

ops:vmov

2006-11-22T15:21:54+02:00

vmov.q/t/p/s Copies vs into vd. Usage: vmov.q/t/p/s vd, vs { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = vs[i]; } clock ticks latency vmov.q/t/p/s 1 0

ops:vmtvc

2007-03-18T02:00:54+02:00

vmtvc Synopsys Copies a scalar vfpu register into a vfpu control register. Type single-cycle instruction Description vmtvc vs.s, vcr { vcr = vs.s; } Prefixes vpfxs vfpxt vpfxd Ignored Ignored Ignored Cycles pitch latency 1 3 VFPU Control Registers register name purpose 128 VFPU_PFXS Source prefix stack 129 VFPU_PFXT Target prefix stack 130 VFPU_PFXD Destin…

ops:vmul

2006-11-22T15:09:53+02:00

vmul.q/t/p/s Multiplies each component of the single precision float vector vs by the same component of vt and stores them into vd. Usage: vmul.q/t/p/s vd, vs, vt { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = vs[i] * vt[i]; } clock ticks latency vmul.q/t/p/s 1 0

ops:vneg

2006-11-22T15:19:16+02:00

vneg.q/t/p/s Changes the sign of each component of the single precision float vector vs and stores them into vd. Usage: vneg.q/t/p/s vd, vs { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = -vs[i]; } clock ticks latency vneg.q/t/p/s 1 0

ops:vpfxd

2008-07-08T23:39:25+02:00

vpfxd [] Alters the writing contents of a single precision float vector vd in the next non-prefix instruction. Can be used as a prefix instruction or as a postfix operand for vd. Usage as prefix instruction: vpfxd ?0, ?1, ?2, ?3 Example as postfix operand:

ops:vpfxs

2008-07-08T23:32:20+02:00

vpfxs [] Alters the reading contents of a single precision float vector vs in the next non-prefix instruction. Can be used as a prefix instruction or as a postfix operand for vs. Usage as prefix instruction: vpfxs ?0, ?1, ?2, ?3 Example as postfix operand:

ops:vpfxt

2008-07-08T23:34:48+02:00

vpfxt [] Alters the reading contents of a single precision float vector vt in the next non-prefix instruction. Can be used as a prefix instruction or as a postfix operand for vt. Usage as prefix instruction: vpfxt ?0, ?1, ?2, ?3 Example as postfix operand:

ops:vrcp

2007-03-18T14:41:02+02:00

vrcp.q/t/p/s Calculates the reciprocal of vs and stores the result in vd. Usage: vrcp.q/t/p/s vd, vs { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = 1.0 / vs[i]; } clock ticks latency vrcp.q/t/p/s ? ?

ops:vrsq

2007-03-18T14:43:26+02:00

vrsq.q/t/p/s Calculates the reciprocal of the square root of vs and stores the result in vd. Usage: vrsq.q/t/p/s vd, vs { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = 1.0 / sqrt( vs[i] ); } clock ticks latency vrsq.q/t/p/s ? ?

ops:vs2i

2007-03-18T14:20:58+02:00

vs2i.p/s Converts two/four packed 16-bit signed short values in vs to two/four 16.16 fixed-point integer values in vd. Usage: vs2i.s vd.p, vs.s { vd.p[0] = ((vs.s[0] ) & 0xffff) << 16; vd.p[1] = ((vs.s[0] >> 16) & 0xffff) << 16; } vs2i.p vd.q, vs.p { vd.q[0] = ((vs.p[0] ) & 0xffff) << 16; vd.q[1] = ((vs.p[0] >> 16) & 0xffff) << 16; vd.q[2] = ((vs.p[1] >> 0) & 0xffff) << 16; vd.q[3] = ((vs.p[1] >> 16) & 0xffff) << 16; }

ops:vscl

2006-11-22T15:16:05+02:00

vscl.q/t/p/s Multiplies each component of the single precision float vector vs by the scalar vs.s and stores them into vd. Usage: vscl.q/t/p/s vd, vs, vt.s { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = vs[i] * vt.s; } clock ticks latency vscl.q/t/p/s 1 0

ops:vsgn

2006-11-22T14:35:36+02:00

vsgn.q/t/p/s Computes the sign of each component of the single precision float vector vs and stores them into vd. Usage: vsgn.q/t/p/s vd, vs { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = (vs[i] < 0.0) ? -1.0 : (vs[i] > 0.0) ? +1.0 : 0.0; } clock ticks latency vsgn.q/t/p/s 1 0

ops:vsub

2006-11-22T15:16:42+02:00

vsub.q/t/p/s Subtracts each component of the single precision float vector vt from the same component of vs and stores them into vd. Usage: vsub.q/t/p/s vd, vs, vt { for (i = 0; i < |q/t/p/s|; ++i) vd[i] = vs[i] - vt[i]; } clock ticks latency vsub.q/t/p/s 1 0

ops:vuc2i

2007-03-18T13:45:29+02:00

vuc2i.s Converts four packed 8-bit unsigned char values in vs to four s.8.23 fixed-point integer values in vd. Usage: vuc2i.s vd.q, vs.s { vd.q[0] = ( ((vs.s[0] ) & 0xff) * 0x01010101) >> 1; vd.q[1] = ( ((vs.s[0] >> 8) & 0xff) * 0x01010101) >> 1; vd.q[2] = ( ((vs.s[0] >> 16) & 0xff) * 0x01010101) >> 1; vd.q[3] = ( ((vs.s[0] >> 24) & 0xff) * 0x01010101) >> 1; }

ops:vus2i

2007-03-18T14:21:31+02:00

vus2i.p/s Converts two/four packed 16-bit unsigned short values in vs to two/four s.16.15 fixed-point integer values in vd. Usage: vus2i.s vd.p, vs.s { vd.p[0] = ((vs.s[0] ) & 0xffff) << 15; vd.p[1] = ((vs.s[0] >> 16) & 0xffff) << 15; } vus2i.p vd.q, vs.p { vd.q[0] = ((vs.p[0] ) & 0xffff) << 15; vd.q[1] = ((vs.p[0] >> 16) & 0xffff) << 15; vd.q[2] = ((vs.p[1] >> 0) & 0xffff) << 15; vd.q[3] = ((vs.p[1] >> 16) & 0xffff) << 15; }